Research Interests

There has been an increased pressure on compilers due to the adoption of higher-level programming languages and development of interesting hardware platforms; modern compilers still rely on human-written optimizations and algorithms requiring expertise and time and are very hard to be correct. My primary research objective is towards building a superoptimization based general-purpose compiler which could compete with current compilers.

Publications:

• Effective use of SMT solvers for Program Equivalence Checking through Invariant Sketching and Query Decomposition. SAT 2018

Conferences attended

• Will be attending Federated Logic Conference 2018, to be held from July 06 to July 19,2018 at Oxford,UK
• Attended Winter School in Software Engineering, held from Dec 11 to Dec 16,2017 at TRDDC,Pune
• Attended SOSP 2017, held from Oct 29 to Oct 31 at Shanghai, China
• Attended APSYS 2017, held on Sept 2-3 at IIT-Bombay
• Attended First Indian SAT+SMT School held during 4-10 Dec, 2016 at TIFR-Bombay.

Education and Work

• 2005 - 2009: BTech in Electronics and Communication Engineering from NIT,Kurukshetra
• 2009 - 2014: R&D Engineer with Bharat Electronics Ltd, Ghaziabad
• 2014 - 2016: Lead R&D Engineer with Samsung R&D Institute, Delhi
• 2016 onwards: PhD Scholar in School of IT at IIT Delhi

shubhani@cse.iitd.ac.in
gupta.shubhani@gmail.com
411, Cloud and HPC Lab, SIT Building,
IIT Delhi, New Delhi- 110016
Phone: +91 9971687222